U.S. Pat. No. 4,656,374 discloses, a low power buffer circuit capable of discriminating the levels of an input logic signal. To provide transistor-transistor-logic (TTL) logic family compatibility, the circuit operates about a reference voltage applied to the gate of an insulated gate field effect transistor to establish an input switching threshold for the buffer circuit appropriate for the desired TTL logic family compatibility. Further, configuring the circuit in such a way that for each static state of an input signal, each current path of the circuit has one nonconducting transistor, power dissipation of the buffer circuit is substantially reduced to zero.
However, low power dissipation is not the only requirement that such buffer circuits should desirably meet. With the ever increasing demand for higher operating speed digital circuits, buffer circuits also having very high-speed response characteristics are desired.